Using DGC

dgc

dgc is the main program of the DGC project. dgc creates a netlist from an abstract description. dgc requires three files:

1. Description of the digital system.
2. Description of the digital cells that should be used to create the netlist (cell library).
3. The created file (netlist).

dgc example.bex -lib default.genlib -oe example.edif

Library options

dgc requires a cell library. A cell library contains simple digital elements that can perform simple boolean operations. A list of these elements must be imported into dgc with the commandline option -lib.

dgc reduces complicated boolean expressions to simple boolean operations. (This process is called synthesis.) Each element of a cell library has a name that usually has some relation to the function of the cell. For example an element that performs a logical and operation between two input lines might have the name AN2, but the name might also be AND2P1 or something else. dgc identifies the function of each element of a cell library and assigns a function name to each cell. The function name is composed of the name of the boolean operation and the number of inputs. Boolean operations are and, nand, or and nor. So the cells AN2 and AND2P1 both will have the same function name and2.

Obviously the type of the elements influences the synthesis result (the netlist). If the cell library does not contain an and2 cell, the result will also not contain an element that performs a logical and operation between two input lines. In some cases it might be useful to remove elements from a cell library. dgc can do this with the option -dcl "list of function names". The following example removes all cells with the function name or2 and or3:

dgc example.bex -lib default.genlib -dcl "or2 or3" -oe example.edif

Netlist options

dgc can write several netlist formats. These are EDIF (-oe), VHDL (-ov) and XNF (-ox).

The EDIF netlist is a very powerful netlist format. Especially EDIF requires a name for some parts of the information that is stored in the netlist.

name of the cell library

dgc reads basic building blocks from a cell library (e.g. default.genlib). The created netlist only contains references to certain cells of this cell library. For further processing of the netlist other tools need to know from which library these cells had been choosen. The commandline option -clib <cell-lib> assigns a used defined name to the EDIF netlist. The example

dgc example.bex -lib default.genlib -clib "CELL_LIB_0.13" -oe example.edif

tells all postprocessing tools that the elements of example.edif are part of the library CELL_LIB_0.13.

name and library name of the created design

The example

dgc example.bex -lib default.genlib -oe example.edif

reads and processes example.bex. EDIF can contain the name of the design so that other tools might also use the same name. The following example tells all postprocessing tools to assume the name myexample for the design that has been created from the specification in example.bex.

dgc example.bex -lib default.genlib -tcell myexample -oe example.edif

EDIF not only requires a name for the design. It also contains a library name for the design. Usually the name and the library name of a design could be any valid string. There is only one little exception: The library name for the design (-tlib) must differ from the name of the cell library (-clib). The following example assigns a name (-tcell) and a library name (-tlib) for the design:

dgc example.bex -lib default.genlib -tcell myexample -tlib mylib -oe example.edif

name of the netlist view

The information stored in an EDIF netlist are grouped within different views. dgc stores exactly one view and assigns the name symbol which seems to be a good default name. If a postprocessing tool requires a different name for the view use the -view command.

Options for EDIF netlist (-oe): The following commandline options can be used to alter the creation of an EDIF netlist:

-clib

The name of the cell library. This name must match an existing technology library.

-tcell

-tlib

A user defined name and library name of the design. The library name must differ from the cell library.

-view

Assign a name to the netlist view of the EDIF file format.

The VHDL netlist format also requires a reference to the cell library. A VHDL netlist will contain the commands

LIBRARY <cell-lib>; USE <cell-lib>.components.all;

where <cell-lib> should be specified with -vlib <cell-lib>. VHDL also requires an entity and architecture name for the design. The entity name can be assigned with -tcell. The name of the architecture is netlist.

Options for VHDL netlist (-ov): The following commandline options can be used to alter the creation of a VHDL netlist:

-vlib

The name of the cell library. This name must match an existing VHDL synthesis or simulation library.

-tcell

A user defined name of the entity.

Logic minimization

Several options affect the minimization of boolean functions.

-optn

-noptn

Enable or disable the net cache algorithm. This procedure ensures that a cell is not used twice for the same input lines.

-optg

-noptg

Enable or disable optimization procedures on the generic netlist.

-optt

-noptt

Enable or disable optimization procedures on the netlist after technology mapping.

-optl

-noptl

Enable or disable the extraction of common subexpressions.

-optm

-noptm

Enable or disable boolean minimization.

Synchronous sequential circuits

If the specification for dgc is a state machine then dgc creates a sequential circuit. The default operation (no -async specified) creates synchronous state machines. This means that memory elements (data-flip-flops) are used to store the current state.

A sequential circuits might have a reset input:

-nrs

Do not generate a reset input.

-rsl

Generate a low aktive reset. This will create an additional input line with the name clr. A logical 0 will force the state machine to stay in the reset state.

-rsh

Generate a high aktive reset. This will create an additional input line with the name clr. A logical 1 will force the state machine to stay in the reset state.

The description of a state machine can be redundant. The commandline option -mis applies a state minimization procedure.

The states of a state machine must encoded to obtain boolean functions for the sequential circuit. There are several encoding techniques: -encsimple, -encfi, -encica and -encicp. Encodung only affect the size of the final circuit.

All options according logic minimization also affect synchronous circuits.

Conclusion:

-nrs

Do not generate a reset input.

-rsl

Generate a low aktive reset.

-rsh

Generate a high aktive reset.

-mis

-nomis

Enable or disable state minimization.

-encsimple

-encfi

-encica

-encicp

Select encoding algorithm.

Asynchronous sequential circuits

One of the key features of dgc is the construction of asynchronous circuits. The synthesis of asynchronous circuits is enabled with the -async commandline option. This option also selects a different state encoding algorithm. Encoding options for synchronous state machines (-encsimple, etc.) are ignored.

Reset behavior and state minimization are controlled in the same way as mentioned in the last section: Use -nrs, -rsl and -rsh to apply a suitable reset. Use -mis for a state minimization.

Additionaly asynchronous state encoding is able to use the output values as state variables. This is selected with -fbo. Using this option is recommended. It will usually reduce the area of the digital circuit.

An asynchronous circuit uses delay elements instead of d-flip-flops. The delay depends on the boolean logic of the sequential circuit. The calculation and the insertion of the delay elements is suppressed by the commandline option -nodlycor. A valid asynchronous circuit requires this delay. Using -nodlycor will create an invalid state machine.

Currently, dgc creates burst-mode asynchronous state machines if the input file is a BMS description. KISS files describe more general state machines. Usuallay it is not possible to create asynchronous state machines from a KISS file, but dgc tries to do so. Indeed dgc does a relaxed checking of the burst-mode properties for KISS input files. The option -bms forces burst-mode properties in a case where the input specification is a KISS file.

All options according logic minimization also affect asynchronous circuits.

Conclusion:

-async

Generate asynchronous circuits.

-nrs

Do not generate a reset input.

-rsl

Generate a low aktive reset.

-rsh

Generate a high aktive reset.

-mis

-nomis

Enable or disable state minimization.

-fbo

-nofbo

Enable or disable the use of output values for state encoding.

-dlycor

-nodlycor

Enable or disable the insertion of delay elements. -bms Force burst-mode check.

Messages

dgc can generate many messages during the synthesis process. The generation of messages is controlled by a level variable that contains a threshold. Messages below the threshold are not generated. The default value for the threshold is 4. Different values can be assigned with -ll <val>. The value 7 suppresses all messages. The value 0 shows all messages.

Analysis

dgc can analyse the capacitance for each transition of a sequential circuit. Results are written as normal messages if the option -cap is used. The capacitance is calculated from the information of the library file. So the unit is the same as in the library file (usually pF).

Capacitance analysis is ignored for pure boolean functions (e.g. BEX, NEX and PLA files)

Delay path construction

dgc can calculate the delay of a digital network. A delay chain of inverter cell is generated with the -dlypath option that is larger than the calculated delay. The construction of the inverter chain is only possible for boolean functions.

dgsop

dgsop is the commandline interface for several algorithms that read boolean expressions. dgsop does not read state machines. dgsop accepts PLA, BEX and NEX files.

A small online help is written to stdout if dgsop is called without any arguments. Some important commands of dgsop include the following:

-op <outputfile>

Write the result as a PLA file.

-ob <outputfile>

Write the result as a BEX file.

-nop <inputfile>

Do nothing. This can be used together with -op and -ob to convert file formats for boolean expressions.

-min <inputfile>

Generate a minimal two level representation of the boolean function in <inputfile>.

-primes <inputfile>

Generate all prime implicants of the boolean function in <inputfile>.