A system for the creation of digital circuits.
Digital circuits can be used to build some kind of hardware.
Often a hardware is an application specific integrated circuit
or a programmable logic array. In this both cases hardware is
created from a 'netlist'. Such a netlist contains information
about the connection of some basic building blocks (gates).
DGC is a system for the creation of netlist files by using an
abstract spezification of digital systems.
The following types of specification are supported:
- Sum of product expression
- Boolean expression
- Numeric expression
- State machine description
- Burst mode specification, Subset of state machine description
- Script language to build hierarchical designs
For the conversion from an abstract description to a netlist,
DGC needs to know what kind of basic building blocks are available.
Such a file is called a gate library.
This is a list of currently supported input formats:
- PLA (.pla, .pl)
- This is a sum of product representation of several
boolean functions. This format is used in the well known
espresso tool (University of California).
- BEX (.bex, boolean expression)
- This is a more readable format for boolean functions.
See example.bex for a description.
- NEX (.nex, numeric expression)
- Extracts boolean functions from mathematical expressions.
See example.nex for a description.
- KISS (.kiss)
- A description of a finite state machine. This file format
is used by the tools KISS, NOVA and others. Some of these
tooles can be found in the SIS package
The file example.kiss can be found in
- BMS (.bms, burst mode spezification)
- Also a file format for the description of finite state machines.
It is a spezial restricted format to describe asynchronous
state machines. A description of the format is included
in the MINIMALIST package (Columbia University)
- DGD (.dgd, digital gate design)
- This is a small script language to import and use all supported
file formats. See the file
for an example.
- EDIF (.edif)
- The elecronic design interchange format (http://www.edif.org/).
This is the most used and known format to store a netlist.
- VHDL-netlist (.vhdl)
- VHDL can be used to store a netlist. This format has been added
to support simulation of the result with a digital VHDL simulator.
- XNF (.xnf)
- There is an experimental Xilinx netlist export filter.
dgc is the main tool of the package. It creates a netlist from the
specified input file.
simfsm is a program to generate support files for fsm simulation.
Its main purpose is to generate stimuli data for finite state machines.
At the moment, only VHDL is supported.
bms2kiss converts a
BMS description into the corresponding KISS description.
The dgc package contains many functions for 2-level boolean minimization
This tool gives access to some of these functions. The idea
dgsop is to provide a clone of the program ESPRESSO.
This document was generated
by Oliver Kraus on May, 22 2002